VHDL实验报告--交通灯

发布于:2021-05-15 00:12:18

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Vhdl1 is port(clk:in std_logic;---时钟信号 led:out std_logic_vector(11 downto 0)); end entity Vhdl1; architecture rtl of Vhdl1 is signal clk1,q:std_logic; signal temp:std_logic_vector(4 downto 0); signal cnt:std_logic_vector(25 downto 0); begin

process(clk)is begin if(clk'event and clk='1')then if(temp="11011")then temp<="00000"; else temp<=temp+1; case temp is when"00000"=>led<="010100100100"; when"00001"=>led<="010100100100"; when"00010"=>led<="010100100100"; when"00011"=>led<="010100100100"; when"00100"=>led<="010100100100"; when"00101"=>led<="001001100100"; when"00110"=>led<="001001100100"; when"00111"=>led<="100010100100"; when"01000"=>led<="100010100100"; when"01001"=>led<="100010100100"; when"01010"=>led<="100010100100"; when"01011"=>led<="100010100100"; when"01100"=>led<="100001001100"; when"01101"=>led<="100001001100"; when"01110"=>led<="100100010100"; when"01111"=>led<="100100010100"; when"10000"=>led<="100100010100"; when"10001"=>led<="100100010100"; when"10010"=>led<="100100010100"; when"10011"=>led<="100100001001";

when"10100"=>led<="100100001001"; when"10101"=>led<="100100100010"; when"10110"=>led<="100100100010"; when"10111"=>led<="100100100010"; when"11000"=>led<="100100100010"; when"11001"=>led<="100100100010"; when"11010"=>led<="001100100001"; when"11011"=>led<="001100100001"; when others=>led<="XXXXXXXXXXXX"; end case; end if; end if; end process; end rtl;


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